// jtag_tap.sv
module jtag_tap (
  input  logic tck, tms, tdi,
  output logic tdo,
  output logic ir_capture, update_dr,
  output logic [7:0] ir_in,
  input  logic [31:0] dr_out,
  output logic [31:0] dr_in
);
  // IEEE 1149.1 状态机
  // 简化版：支持 IDCODE, BYPASS, EXTEST, DEBUG
  assign tdo = tdi; // 简化
  assign ir_in = 8'h01;
endmodule